Steered by CMOS scaling, which allows improvements in the performance of digital circuits while lowering the cost, wireless radios are becoming increasingly digital insensitive. This evolution has revived the suggestion of shifting the signal conditioning of an analog receiver chain to the digital domain by placing a high speed ADC as close as possible to the antenna (see FIG. 1). By digitizing at RF, this architecture becomes a native software radio, nicely scaling with CMOS technologies. Obviously, the very high speed and the large dynamic range required make the design of the ADC very challenging.
Several chip implementations indicate that the best topology in terms of minimum power required to receive a given signal bandwidth at a given resolution for this RF ADC architecture is an RF bandpass sigma-delta converter since it can digitize a high-frequency band-limited signal with high resolution. Traditionally, bandpass sigma-delta ADC's are centered on integer fractions of the sampling clock. To receive e.g. the full ISM band at 2.4 GHz, the sampling clock should be 9.6 GHz in a Fs/4 structure.
Several single loop RF bandpass sigma-delta ADC's report effective number of bits (ENOB) of 6 to 8 bits over a signal bandwidth of around 80 MHz. To be fully compatible with classical receiver architectures, this resolution needs to be increased. This can be done by 1) increasing the oversampling ratio (OSR) by increasing the sampling frequency (Fs); 2) increasing the order of the sigma-delta converter, or 3) increasing the ENOB in the embedded ADC in a sigma-delta converter. The first method is limited for RF BP sigma-delta converters, as the system already operates at its limit in terms of sampling frequency. Stability considerations of higher order sigma-delta converters limit the increase of the order since sigma delta converters with an order larger than 2 have more chance to be unstable. However, the cascaded sigma-delta approach (FIG. 2) achieves a higher overall effective order sigma-delta converter by cascading low-order (1st or 2nd order) sigma-delta converters which are inherently stable, leading to an effective higher order.
A so called “2-1” cascade sigma-delta e.g. consists of a first 2nd order stage and a second 1st order stage. The quantization error (noise) of the first stage is fed into the second stage and is digitized. Digital cancellation filters then combine the outputs of the two stages and reduce the quantization noise of the first stage, so that only the quantization noise of the 2nd stage remains. In this way a 3rd order noise transfer function (NTF) is created but with the stability of a 2nd order sigma-delta, which is unconditionally stable.